It is desirable to produce as large a yield of semiconductor devices per wafer in as short a time as possible. To increase the speed of device manufacture, the layout for several integrated circuit (IC) chips is formed at the same time. Typically, a reticle having a grid of several layouts is stepped or scanned across the entire surface of the wafer while radiation is passed through the reticle to a resist layer on the wafer. The fabrication of IC chips in the perimeter regions of the wafer using this approach is problematic, however.
There are limitations in the focusing ability of lithography equipment and topographic variations in the outer annulus region of the wafer at the wafer edge. This results in the production of poorly-defined vias and trench features in certain IC chips located near or at the annulus. In addition, metal deposition procedures in the annulus region are not as uniform as for the interior portions of the wafer. Consequently, lithographic printing and etching of patterns and deposition of conductive lines in the annulus region can result in the production of partially completed device features.
The partially completed device features can serve as particle traps for debris produced during the electrode chemical deposition (ECD) of metals and chemical mechanical polishing (CMP). Moreover, the debris can dislodge and contaminate semiconductor devices being fabricated on interior portions of the wafer, thereby reducing device yields. In a similar fashion, portions of the partially completed device features can peel off during subsequent processing steps and contaminate other portion of the wafer.
To reduce these problems, the printing and etching of device features into the wafer is followed by several remedial procedures to mitigate the undesirable consequence of producing the partially completed device features. These remedial procedures themselves, however, have undesirable side effects. Consider, for example, wafer edge exclusion (WEE), one procedure typically used to reduce wafer contamination from the above-described partially complete features. Typically a wafer is exposed to lithographic printing and etching as discussed above, followed by the WEE process. The WEE process involves exposing a band of resist located on the perimeter of the wafer to form a trench. The trench is filled with a metal to prevent waste material from becoming lodged in the trench and contaminating other portions of the wafer. The resulting metal band, however, can cause electrical arcing during subsequent processing steps. In addition, vias deposited over the metal band are prone to peeling.
To reduce the deleterious side effects associated with the WEE process, an edge bead removal (EBR) procedure, such as chemical etching, is applied to take off the metal band. Typically, however, there is a slight spatial mismatch between the positioning of metal remaining in the outer trench after the WEE process, and the regions of metal taken off during the EBR procedure. An excessive EBR spatial mismatch can result in the undesirable formation of open trenches. Alternatively, a misaligned EBR can leave a residual metal band, with problems ensuing similar to that discussed above. To reduce problems remaining after WEE and EBR, a further procedure to blade off corner chips is done. The blade-off procedure, however, reduces the yield of IC chips because it undesirably blocks the production of all IC chips around the perimeter of the wafer.
Accordingly, what is needed in the art is a flexible low cost method to avoid printing undesired patterns at the wafer's edge, while not introducing additional problems into semiconductor device manufacturing processes.